用VHDL设计D触发器

伙计分点少了 呵呵 不过还是帮你一下吧 源程序和仿真波形： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity m6 is port(clk,rst:in std_logic; q: out std_logic_vector(2 downto 0)); end m6; architecture bhv of m6 is type states is(st0,st1,st2