用VHDL的if语句设计一个4位D触发器

ENTITY dff_4 IS PORT(clk: IN bit; d: IN bit_vector(3 DOWNTO 0); q,q_n: OUT bit_vector(3 DOWNTO 0)); END dff_4; ARCHITECTURE bhv OF dff_4 IS SIGNAL q_s: bit_vector(3 DOWNTO 0); BEGIN PROCESS(clk) BEG