请问用if写出四选一多路选择器的vhdl的设计，怎么写？

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sixuanyi is port(clk:in std_logic; sel:in std_logic_vector(1 downto 0); a,b,c,d:out std_logic); end sixuanyi; architecture of4 of sixuanyi is signal a