状态机 实现对101101的检测 verilog

module seq(input clk, input rst, input i, output o);
reg [0:5] seq;
assign o = seq == 6'b101101 ? 1'b1 : 1'b0;
always @(posedge clk, posedge rst) begin
if(rst) begin
seq <= 6'b0;
e