试设计一个下降沿触发D触发器的VHDL程序

Library IEEE; USE IEEE.std_logic_1164.ALL; ENTITY my_dff IS PORT(clk,d: IN std_logic; q,q_n: OUT std_logic); END my_dff; ARCHITECTURE one OF my_dff IS BEGIN PROCESS(clk) VARIABLE q_temp: std_logic; BEG