求用vhdl语言做个全加器的程序

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; --USE IEEE.STD_LOGIC_unsigned.ALL; --USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY if_adder IS PORT (a,b,c : IN STD_LOGIC; co, so : out STD_LOGIC); END ENTITY if_adder ; ARCHITECTURE fh1 OF if_adder